library ieee;
use IEEE.STD_LOGIC_TEXTIO.all;
use STD.TEXTIO.all;
use ieee.std_logic_1164.all;


entity tb_programCounter is
end tb_programCounter;

architecture testbench_arch of tb_programCounter is
  component programCounter is
  port
    (
      -- Write data input port    
      clk        : in  std_logic;
      nReset     : in  std_logic;
      sel        : in  std_logic_vector(1 downto 0);
      inst       : in  std_logic_vector (31 downto 0);
      busA       : in  std_logic_vector (31 downto 0);
      -- read port 2
      pcplusfour : out std_logic_vector (31 downto 0);
      pcout      : out std_logic_vector (31 downto 0)
      );
end component;


  signal pcplusfour, pcout,  inst, busA   : std_logic_vector (31 downto 0);
  signal sel             : std_logic_vector (1 downto 0);
  signal nReset : std_logic;
  signal clk : std_logic := '0';

  constant zero : std_logic_vector := "00000000000000000000000000000000";
  constant v1   : std_logic_vector := "00000000000000000000000000000001";
  constant v2   : std_logic_vector := "00000000000000000001001001110001";
  constant v3   : std_logic_vector := "00000000000000000110001000011111";
  constant v4   : std_logic_vector := x"FFFFFFFF";


  procedure println( output_string : in string ) is
    variable lout                  :    line;
  begin
    WRITE(lout, output_string);
    WRITELINE(OUTPUT, lout);
  end println;

  procedure printlv( output_bv : in std_logic_vector ) is
    variable lout              :    line;
  begin
    WRITE(lout, output_bv);
    WRITELINE(OUTPUT, lout);
  end printlv;


begin
  DUT : programCounter
    port map (
      busA => busA,
      pcout => pcout,
      inst => inst,
      pcplusfour => pcplusfour,      
      sel   => sel,
      nReset => nReset,
      clk    => clk
      );


  process
    begin
      wait for 50 ns;
      clk <= not clk;
    end process;

    
  process

  begin

    println("");
    println("Starting Test");

    sel <= "00";
    inst <= zero;
    busA <= zero;
    
    -- reset                            --------------
    nReset <= '0';
    wait for 100 ns;
    nReset <= '1';
    -- --------------------
    wait for 500 ns;

    inst <= v4;
    wait for 500 ns;
    
    

    
    -- end simulation
    wait;

  end process;
end testbench_arch;


